The present invention relates generally to digital and analog circuit design. More particularly, the present invention relates to a digital circuit that combines the functionality of two parallel XOR gates in series with a summer/multiplexer.
High speed digital data communication devices utilize phase detector circuits to produce an output voltage proportional to the frequency or phase differences of two input signals. During frequency acquisition, the frequency of an incoming data signal is compared to the frequency of an external reference clock. During phase acquisition, incoming data is compared to a derived version of an internal reference clock (usually generated by a voltage controlled oscillator). FIG. 1 is a block diagram of a prior art digital circuit 100 that may be utilized in a phase detector application. Circuit 100 includes an XOR component 102, an XOR component 104, a summer 106 that receives the outputs of the two XOR components, and a multiplexer 108 connected in series with summer 106. One input to XOR component 102 is a data signal 110 that represents a first sampled version of an input data signal, and the other input to XOR component 102 is a data signal 112 that represents a second sampled version of the input data signal. Similarly, one input to XOR component 104 is a data signal 114 that represents a third sampled version of the input data signal, and the second input to XOR component 104 is a data signal 116 that represents a fourth sampled version of the input data signal.
The output of XOR component 102 serves as one input 118 to summer 106, and the output of XOR component 104 serves as a second input 120 to summer 106. Summer 106 functions to generate different voltage levels in response to the logic levels of inputs 118/120. The output of summer 106 represents a phase detect signal 122. If both inputs 118/120 are logic low, then phase detect signal 122 exhibits a relatively low voltage level. If both inputs 118/120 are logic high, then phase detect signal 122 exhibits a relatively high voltage level. If one input is a logic low and the other is a logic high, then phase detect signal 122 exhibits a relatively intermediate voltage level.
Circuit 100 also receives a frequency detect signal 124 from a frequency detection circuit (not shown) and a frequency lock signal 126 (frequency lock signal 126 serves as a selection signal for multiplexer 108). Ultimately, circuit 100 generates an output signal 128xe2x80x94the output of multiplexer 108. Circuit 100 utilizes output signal 128 to adjust the frequency and phase of a clock signal 130 generated by a voltage controlled oscillator (VCO) 132. Initially, circuit 100 selects frequency detect signal 124 (using multiplexer 108) for use as output signal 128, which controls the operation of VCO 132 such that the frequency of clock signal 130 matches the frequency of the incoming data signal. Thereafter, circuit 100 selects phase detect signal 122 (using multiplexer 108) for use as output signal 128, which controls the operation of VCO 132 such that the phase of clock signal 130 is properly aligned relative to the phase of the input data signal.
FIG. 2 is a schematic representation of circuit 100 as implemented in a practical device. In a practical high speed application, circuit 100 handles differential input signals and generates a single-ended output signal 128. Accordingly, XOR input signal 110 is represented by a positive or xe2x80x9ctruexe2x80x9d signal (A1p) and a negative or xe2x80x9ccomplementaryxe2x80x9d signal (A1N), XOR input signal 112 is represented by a positive signal (B1p) and a negative signal (B1N), XOR input signal 114 is represented by a positive signal (A2P) and a negative signal (A2N), and XOR input signal 116 is represented by a positive signal (B2P) and a negative signal (B2N) Likewise, frequency detect signal 124 is represented by a positive signal (FDP) and a negative signal (FDN), and frequency lock signal 126 is represented by a positive signal (FLP) and a negative signal (FLN).
Circuit 100 is implemented such that: the transistors, resistors, and other features of XOR component 102 define one physically distinct circuit; the transistors, resistors, and other features of XOR component 104 define a second physically distinct circuit; and the transistors, resistors, and other features of summer 106 and multiplexer 108 combine to define a third physically distinct circuit. This third circuit is shown in FIG. 2 as a summer/MUX component 134. In this regard, FIG. 3 is a schematic of a prior art XOR component 300, and FIG. 4 is a schematic of a prior art summer/MUX component 400. XOR component 300 is designed to operate as an independent device that generates a differential XOR output 302 based upon two differential input signals 304/306, and summer/MUX component 400 is designed to operate as an independent device that receives two differential input signals 402/404 (corresponding to the outputs of two XOR components), a differential frequency detect signal 406, and a differential frequency lock signal 408. Summer/MUX component 400 generates an output signal 410 based upon either frequency detect signal 406 or a sum of input signals 402/404, under the control of frequency lock signal 408. Referring back to FIG. 2, in a practical implementation, XOR component 102 and XOR component 104 are each physically connected to summer/MUX component 134 using conductive traces configured to carry signals 118/120 between the components.
Circuit 100, while suitable for relatively low speed data communication applications (e.g., those handling data rates of 2.5 Gbps or less), is not suitable for relatively high speed applications (e.g., those handling data rates up to or beyond 40 Gbps). In very high speed applications, the limited bandwidth of circuit 100 adversely affects its performance. Furthermore, circuit 100 requires separate current sources (one or more for each XOR component and one or more for summer/MUX component 134), which results in an inefficient use of operating power.
A circuit according to the present invention includes the functionality of two XOR components integrated with the functionality of a summer and a multiplexer. The combined function of the circuit is equivalent to distinct XOR components connected in series with a distinct summer/multiplexer component. The integrated configuration enables the circuit to achieve higher bandwidth than equivalent prior art circuits, while using less operating power.
The above and other aspects of the present invention may be carried out in one form by an integrated device having: a reference voltage node; an output voltage node; a first XOR arrangement coupled to the reference voltage and output voltage nodes, where the first XOR arrangement is configured to perform an XOR operation based upon a first input signal and a second input signal; a second XOR arrangement coupled to the reference voltage and output voltage nodes, where the second XOR arrangement is configured to perform an XOR operation based upon a third input signal and a fourth input signal; an input arrangement coupled to the reference voltage and output voltage nodes, where the input arrangement is configured to receive a fifth input signal; and a MUX arrangement coupled to the first XOR arrangement, to the second XOR arrangement, and to the input arrangement, where the MUX arrangement is configured to select either the input arrangement or the first and second XOR arrangements for operation in response to a select signal.